Table of Contents Author Guidelines Submit a Manuscript
International Journal of Reconfigurable Computing
Volume 2011, Article ID 601986, 22 pages
http://dx.doi.org/10.1155/2011/601986
Research Article

Exploring Online Synthesis for CGRAs with Specialized Operator Sets

Chair for Embedded Systems, Dresden University of Technology, Nöthnitzer Straße 46, 01187 Dresden, Germany

Received 10 August 2010; Revised 16 December 2010; Accepted 10 February 2011

Academic Editor: Michael Hübner

Copyright © 2011 Stefan Döbrich and Christian Hochberger. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. S. Gatzka and C. Hochberger, “The AMIDAR class of reconfigurable processors,” Journal of Supercomputing, vol. 32, no. 2, pp. 163–181, 2005. View at Publisher · View at Google Scholar
  2. S. Gatzka and C. Hochberger, “The organic features of the AMIDAR class of processors,” in Proceedings of the International Conference on Automation, Robotics and Control Systems (ARCS '05), pp. 154–166, 2005.
  3. S. Gatzka and C. Hochberger, “Hardware based online profiling in AMIDAR processors,” in Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS '05), p. 144b, April 2005. View at Publisher · View at Google Scholar
  4. S. Döbrich and C. Hochberger, “Low-complexity online synthesis for amidar processors,” International Journal of Reconfigurable Computing, vol. 2010, Article ID 953693, 15 pages, 2010. View at Publisher · View at Google Scholar
  5. S. Döbrich and C. Hochberger, “Practical resource constraints for online synthesis,” in Proceedings of the 5th International Workshop on Reconfigurable Communication-Centric Systems on Chip (ReCoSoC '10), pp. 51–58, 2010.
  6. C. Hochberger, R. Hoffmann, K.-P. Volkmann, and S. Waldschmidt, “The cellular processor architecture CEPRA-1X and its conguration by CDL,” in Proceedings of the IEEE International Symposium on Parallel and Distributed Processing (IPDPS '00), pp. 898–905, 2000.
  7. E. Sotiriades and A. Dollas, “A general reconfigurable architecture for the BLAST algorithm,” Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 48, no. 3, pp. 189–208, 2007. View at Publisher · View at Google Scholar
  8. J. R. Hauser and J. Wawrzynek, “Garp: a MIPS processor with a reconfigurable coprocessor,” in Proceedings of the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), pp. 12–21, April 1997.
  9. Y. Li, T. Callahan, E. Darnell, R. Harr, U. Kurkure, and J. Stockwood, “Hardware-software co-design of embedded reconfigurable architectures,” in Proceedings of the 37th Design Automation Conference (DAC '00), pp. 507–512, June 2000.
  10. N. Kasprzyk and A. Koch, “Advances in compiler construction foradaptive computers,” in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, pp. 26–29, Las Vegas, Nev, USA, 2001.
  11. A. Koch and N. Kasprzyk, “High-level-language compilation for reconfigurable computers,” in Proceedings of the International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC '05), pp. 1–8, 2005.
  12. Y. Ha, R. Hipik, S. Vernalde et al., “Adding hardware support to the HotSpot Virtual machine for domain specific applications,” in Proceedings of the International Conference on Field Programmable Logic (FPL '02), pp. 1135–1138, 2002.
  13. C. Ebeling, D. C. Cronquist, and P. Franklin, “RaPiD—reconfigurable pipelined datapath,” in Proceedings of the International Conference on Field Programmable Logic (FPL '96), pp. 126–135, 1996.
  14. Y. Chou, P. Pillai, H. Schmit, and J. P. Shen, “PipeRench implementation of the instruction path coprocessor,” in Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO '00), pp. 147–158, Monterey, Calif, USA, December 2000.
  15. R. W. Hartenstein, M. Herz, T. Hoffmann, and U. Nageldinger, “Mapping applications onto reconfigurable Kress Arrays,” in Proceedings of the International Conference on Field Programmable Logic (FPL '99), pp. 385–390, 1999.
  16. V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, and M. Weinhardt, “PACT XPP—a self-reconfigurable data processing architecture,” Journal of Supercomputing, vol. 26, no. 2, pp. 167–184, 2003. View at Publisher · View at Google Scholar
  17. B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins, “Exploiting loop-level parallelism on coarse-grained reconfigurable architecture susing modulo scheduling,” in Proceedings of the Design, Automation and Test in Europe (DATE '03), pp. 10296–10301, 2003.
  18. F. Bouwens, M. Berekovic, B. De Sutter, and G. Gaydadjiev, “Architecture enhancements for the ADRES coarse-grained reconfigurable array,” in Proceedings of the 3rd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC '08), pp. 66–81, Springer, Berlin, Germany, 2008. View at Publisher · View at Google Scholar
  19. B. Mei, S. Vernalde, D. Verkest, H. De Man, and R. Lauwereins, “ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix,” in Proceedings of the International Conference on Field Programmable Logic (FPL '03), pp. 61–70, 2003.
  20. L. Bauer, M. Shafique, S. Kramer, and J. Henkel, “RISPP: rotating instruction set processing platform,” in Proceedings of the 44th Design Automation Conference (DAC '07), pp. 791–796, June 2007. View at Publisher · View at Google Scholar
  21. R. Lysecky and F. Vahid, “Design and implementation of a MicroBlaze-based warp processor,” Transactions on Embedded Computing Systems, vol. 8, no. 3, pp. 1–22, 2009. View at Publisher · View at Google Scholar
  22. A. C. S. Beck and L. Carro, “Dynamic reconfiguration with binarytranslation: breaking the ILP barrier with software compatibility,” in Proceedings of the Design Automation Conference (DAC '05), pp. 732–737, 2005.
  23. H. Corporaal, Microprocessor Architectures: From VLIW to TTA, John Wiley & Sons, New York, NY, USA, 1997.
  24. S. Gatzka and C. Hochberger, “A new general model for adaptive processors,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '04), pp. 52–60, June 2004.
  25. S. Vassiliadis and D. Soudris, Eds., Fine- and Coarse-Grain Reconfigurable Computing, Springer, New York, NY, USA, 2007.
  26. S. Döbrich and C. Hochberger, “Towards dynamic software/hardware transformation in AMIDAR processors,” It—Information Technology, vol. 50, no. 5, pp. 311–316, 2008. View at Google Scholar
  27. S. Döbrich and C. Hochberger, “Effects of simplistic online synthesis for AMIDAR processors,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig '09), pp. 433–438, December 2009. View at Publisher · View at Google Scholar
  28. S. Döbrich and C. Hochberger, “Predicting hardware acceleration through object caching in AMIDAR processors,” in Proceedings of the International Conference on Automation, Robotics and Control Systems (ARCS '10), pp. 162–171, 2006.