International Journal of Reconfigurable Computing

Research Article

FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition

Table 2

Method A. device utilization on Virtex 5 SX95T FPGA (+did not meet timing for 266 MHz.).
  Single core 2 cores 8 cores 16 cores 32 cores 64 core
Occupied Slices
Slice LUTs
Slice Registers
BlockRam (Kb)
DSP48es