Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems

Table 2

Fixed parameters for the exploration of the impact of the clock frequency, the processor configuration, and the task distribution on the performance, power dissipation, and energy consumption.

Impact of	Fixed parameters	Variable parameters
Clock frequency	(i) Algorithm: NCC	(i) Clock frequency: 40–100 MHz
	(ii) Processor configuration: default (5-stage pipeline, no AU, no FPU)	(ii) FPGA: Virtex-4, Virtex-5
	(iii) # of processors: 1
Processor configuration	(i) Clock frequency: 100 MHz	(i) Processor configurations: (default, AU, RP, RP + AU) ± FPU
	(ii) No. of processors: 1	(ii) Algorithm: NCC, Quicksort, DIALIGN, ANN
		(iii) FPGA: Virtex-4, Virtex-5
Task distribution	(i) Execution time = execution time of a uniprocessor design at 100 MHz	(i) Application partitioning
	(ii) Processor configuration: 5-stage pipeline, integer multiplier, pattern comparator	(ii) Algorithm: NCC, Quicksort, DIALIGN
	(iii) No. of processors: 2
	(iv) FPGA: Virtex-4