A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance

Algorithm 1

Placement frontend (simultaneous scheduling and mapping).

Input:  ReadyNodeSet, FreePESet, current schedule step S

Output:   MappedNodeSet

(1) for each 𝑃𝐸_𝑖 in FreePESet  {CandidateNodeSet(PE_i) = {empty};}

(2) for   each node n in ReadyNodeSet {

(3) CapablePESet(n) = all PE capable of the function of n;

(4) S_src1 = the time when n’s operand 1 is produced;

(5) L_src1 = the PE where n’s operand 1 is stored;

(6) S_src2 = the time when n’s operand 2 is produced;

(7) L_src2 = the PE where n’s operand 2 is stored;

  //all PEs which can be reached within

  //(S-S_src1) cycles from PE L_src1;

(8) RoutableSet1 = RoutableSet(L_src1, (S-S_src1));

  //all PEs which can be reached within

  //(S-S_src2) cycles from PE L_src2;

(9) RoutableSet2 = RoutableSet(L_src2, (S-S_src2));

(10) CandidatePESet = RoutableSet1 ∩RoutableSet2

        ∩FreePESet ∩CapablePESet(n);

(11) for  each PE_i in CandidatePESet{Add 𝑛 to CandidateNodeSet (𝑃𝐸_𝑖);}

(12) }

(13) MappedNodeSet = {empty};

(14) for  each 𝑃𝐸_𝑖 in CandidatePESet{

(15) Sort all nodes in CandidateNodeSet (𝑃𝐸_𝑖) according to criticality;

(16) M = most critical from CandidateNodeSet and

     M ∉MappedNodeSet;

(17) Place 𝑀 on PE_i at schedule step S;

(18) Insert 𝑀 into MappedNodeSet;

(19) Remove 𝑀 from ReadyNodeSet;

(20) }