Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency

Table 3

Complexity comparison of proposed design with existing design variants.

Existing design			% Savings
Circular CORDIC	Area	Latency^1	Area^2	Latency^3
Conventional	73585	32	52.79	68.75
Scaling-free [13]	66273	28	47.58	64.28
ESF-CORDIC [16]	51264	25	32.23	60

¹Latency is defined in terms of number of pipelining stages required by the design.
²The gate count of the proposed design is 34739.
³The latency of the proposed design is 10.