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International Journal of Reconfigurable Computing
Volume 2012, Article ID 236372, 13 pages
Research Article

Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems

1Department of Electrical Engineering, CINVESTAV-GDL, 45019 Zapopan, JAL, Mexico
2Department of Electronic Engineering, UDG-CUCEI, 44430 Guadalajara, JAL, Mexico
3Department of Electrical Engineering, CINVESTAV-DF, 07630 Mexico City, DF, Mexico

Received 4 May 2012; Accepted 17 September 2012

Academic Editor: René Cumplido

Copyright © 2012 E. Romero-Aguirre et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper, a configurable superimposed training (ST)/data-dependent ST (DDST) transmitter and architecture based on array processors (APs) for DDST channel estimation are presented. Both architectures, designed under full-hardware paradigm, were described using Verilog HDL, targeted in Xilinx Virtex-5 and they were compared with existent approaches. The synthesis results showed a FPGA slice consumption of 1% for the transmitter and 3% for the estimator with 160 and 115 MHz operating frequencies, respectively. The signal-to-quantization-noise ratio (SQNR) performance of the transmitter is about 82 dB to support 4/16/64-QAM modulation. A Monte Carlo simulation demonstrates that the mean square error (MSE) of the channel estimator implemented in hardware is practically the same as the one obtained with the floating-point golden model. The high performance and reduced hardware of the proposed architectures lead to the conclusion that the DDST concept can be applied in current communications standards.