International Journal of Reconfigurable Computing / 2012 / Article / Tab 1

Research Article

Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems

Table 1

Synthesis results of the ST/DDST transmitter.

FPGA resourceUsedAvailableUtilization

Frequency160.12MHz
Slice registers14169120<1%
Slice LUTs43769120<1%
Fully used LUT-FF pairs13444430%
IOBs466407%
BRAMs41482%