Research Article
A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection
Table 2
Synthesis results for VEH node components.
| Module | LUT | Reg. bits | BRAM |
| Ring interface | 976 | 2,048 | 20 | PR controller | 722 | 544 | 4 | VEH section with | 15,494 | 6,426 | 120 | 24 slots (w/o VEHs) |
| Total incl. MIG, | 19,540 | 12,428 | 150 | without VEHs | In % of LX155T | 20 | 12 | 70 |
|
|