On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors

Table 2

Excerpt from metrics requested by the candidate estimation process from PivPav circuit library for the XC4VFX100-FF1152-10 FPGA device.

HW Oper.	𝑃𝑝	𝐿𝑝	Max FRQ after PAR	FF	LUT	Slice	BUF	DSP
	#	ns	[MHz]	#	#	#	#	#
mul	1	24.81	40.3	66	76	46	103	0
add	1	32.15	31.1	66	377	250	103	5
mul	10	7.31	136.8	66	134	150	103	4
add	7	7.19	139.0	66	556	326	103	4