Research Article
On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors
Table 3
Results of hardware estimation process for DFGs presented in Figures
3(b) and
3(d) implemented with two different sets of operators found in Table
2.
| | | Sequential datapath (Figure 3(b)) | Highly pipelined sequential datapath (Figure 3(d)) |
| | [ns] | 24.81 and 32.15 | 7.31 and 7.19 | | [ns] | 32.15 | 7.31 | | # | 3 and 2 | 24 and 17 | | # | 3 | 24 | | # | 1.30 | 1.30 | | [ns] | 125.39 | 228.07 |
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