On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors

Table 7

Constant overheads involved in the ASIP-SP. C2V corresponds to the Netlist Generation phase in Figure 2. Syn, Xst, Tra, and Bitgen are the FPGA CAD tool flow processes and correspond to the syntax check, synthesis, translate, and partial reconfiguration bitstream generation processes, respectively, which can be found in the third phase in Figure 2.

	C2V [s]	Syn [s]	Xst [s]	Tra [s]	Bitgen [s]	Sum [s]
Average	3.22	4.22	10.60	8.99	151.00	178.03
Stdev	0.10	0.10	0.23	1.22	2.43