Research Article
A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication
Table 2
Modular multiplier performance.
| Field length
| Computation time
(cycles) | Max. clock frequency
(MHz) | Area
(slices, DSPs) | Latency per iteration
s) | System performance
(PA/s) | ECC core area
(slices, DSPs) |
| | 8 | 21 | 181 | 263, 18 | 1.24 (237 cycles) | 808 K | 5199, 114 | | 16 | 14 | 181 | 217, 10 | 0.790 (151 cycles) | 1.27 M | 4862, 66 | | 32 | 7 | 104 | 253, 20 | 1.09 (114 cycles) | 913 K | 5229, 130 | | 64 | 3 | 68 | 370, 36 | 1.17 (80 cycles) |
854 K | 5776, 214 |
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