International Journal of Reconfigurable Computing / 2012 / Article / Tab 4

Research Article

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

Table 4

Performance of one to eight BLAST cores running in a PowerPC 440 Redsharc system. 100 MHz SSN, BSN, and BLAST Kernel Clocks.

CoresLoad queriesSpeedup BLAST exec.Speedup Read resultsSpeedup Total time Total speedup

1 1x 1x 1x 1x
2 1x 2x 1.19x 1.73x
4 1x 3.98x 1.28x 2.71x
8 1x 7.95x 1.36x 3.81x

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