International Journal of Reconfigurable Computing / 2012 / Article / Tab 5

Research Article

Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

Table 5

Performance of one to eight BLAST cores running in a Microblaze Redsharc system. 100 MHz SSN, BSN, and BLAST Kernel Clocks.

Cores Load queries Speedup BLAST Exec. Speedup Read results Speedup Total time Total speedup

1
2
4
8

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