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International Journal of Reconfigurable Computing
Volume 2012, Article ID 915178, 12 pages
http://dx.doi.org/10.1155/2012/915178
Research Article

NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada

Received 30 April 2011; Revised 22 August 2011; Accepted 27 August 2011

Academic Editor: Viktor K. Prasanna

Copyright © 2012 Kaveh Aasaraai and Andreas Moshovos. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Kaveh Aasaraai and Andreas Moshovos, “NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution,” International Journal of Reconfigurable Computing, vol. 2012, Article ID 915178, 12 pages, 2012. https://doi.org/10.1155/2012/915178.