International Journal of Reconfigurable Computing

Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools

Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Self-Adaptive On-Chip System Based on Cross-Layer Adaptation Approach

Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform

An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization

Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs

Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding

Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm

Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)

Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)

Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines

Fully Pipelined Implementation of Tree-Search Algorithms for Vector Precoding

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units

International Journal of Reconfigurable Computing

Table of Contents

Table of Contents: 2013

Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools

Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

Self-Adaptive On-Chip System Based on Cross-Layer Adaptation Approach

Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform

An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization

Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs

Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding

Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm

Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)

Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)

Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines

Fully Pipelined Implementation of Tree-Search Algorithms for Vector Precoding

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units