Table of Contents Author Guidelines Submit a Manuscript
International Journal of Reconfigurable Computing
Volume 2013, Article ID 140234, 9 pages
Research Article

Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding

1Department of Electrical and Computer Engineering, University of Dayton, Kettering Laboratory, Room 341, 300 College Park, Dayton, OH 45469, USA
2University of Dayton Research Institute, 300 College Park, Dayton, OH 45469, USA
3Air Force Research Laboratory Sensors Directorate, Wright-Patterson Air Force Base, OH, USA

Received 12 February 2013; Revised 6 May 2013; Accepted 29 May 2013

Academic Editor: René Cumplido

Copyright © 2013 John M. McNichols et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a novel implementation of the JPEG2000 standard as a system on a chip (SoC). While most of the research in this field centers on acceleration of the EBCOT Tier I encoder, this work focuses on an embedded solution for EBCOT Tier II. Specifically, this paper proposes using an embedded softcore processor to perform Tier II processing as the back end of an encoding pipeline. The Altera NIOS II processor is chosen for the implementation and is coupled with existing embedded processing modules to realize a fully embedded JPEG2000 encoder. The design is synthesized on a Stratix IV FPGA and is shown to out perform other comparable SoC implementations by 39% in computation time.