Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units

Table 4

Execution times for several implementations of the pattern detector for megablocks.

# Addrs	Execution times (ms)
	HM@50; MHz	MB@50; MHz	Cortex-A8@1 GHz	Speedup; (HM versus; MB/HM versus A8)
12	0.0002	2.7	0.6	11,251/2,500
24	0.0005	5.7	1.3	11,963/2,708
48	0.0010	14.0	2.8	14,594/2,917
96	0.0019	30.8	5.9	16,036/3,073
192	0.0038	64.3	12.5	16,757/3,255
384	0.0077	131.5	24.8	17,118/3,229
768	0.0154	265.7	78.7	17,298/5,124