International Journal of Reconfigurable Computing / 2013 / Article / Tab 4

Research Article

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units

Table 4

Execution times for several implementations of the pattern detector for megablocks.

# Addrs Execution times (ms)
HM@50
MHz
MB@50
MHz
Cortex-A8@1 GHz Speedup
(HM versus
MB/HM versus A8)

120.00022.70.611,251/2,500
240.00055.71.311,963/2,708
480.001014.02.814,594/2,917
960.001930.85.916,036/3,073
1920.003864.312.516,757/3,255
3840.0077131.524.817,118/3,229
7680.0154265.778.717,298/5,124

We are committed to sharing findings related to COVID-19 as quickly as possible. We will be providing unlimited waivers of publication charges for accepted research articles as well as case reports and case series related to COVID-19. Review articles are excluded from this waiver policy. Sign up here as a reviewer to help fast-track new submissions.