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International Journal of Reconfigurable Computing
Volume 2013, Article ID 428078, 10 pages
Research Article

Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools

1INDI Department, Vrije Universiteit Brussel, 1050 Brussels, Belgium
2ELIS Department, Ghent University, 9000 Ghent, Belgium
3ETRO Department, Vrije Universiteit Brussel, 1050 Brussels, Belgium

Received 30 September 2013; Accepted 27 November 2013

Academic Editor: João Cardoso

Copyright © 2013 Bruno da Silva et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The potential of FPGAs as accelerators for high-performance computing applications is very large, but many factors are involved in their performance. The design for FPGAs and the selection of the proper optimizations when mapping computations to FPGAs lead to prohibitively long developing time. Alternatives are the high-level synthesis (HLS) tools, which promise a fast design space exploration due to design at high-level or analytical performance models which provide realistic performance expectations, potential impediments to performance, and optimization guidelines. In this paper we propose the combination of both, in order to construct a performance model for FPGAs which is able to visually condense all the helpful information for the designer. Our proposed model extends the roofline model, by considering the resource consumption and the parameters used in the HLS tools, to maximize the performance and the resource utilization within the area of the FPGA. The proposed model is applied to optimize the design exploration of a class of window-based image processing applications using two different HLS tools. The results show the accuracy of the model as well as its flexibility to be combined with any HLS tool.