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International Journal of Reconfigurable Computing
Volume 2013, Article ID 428078, 10 pages
http://dx.doi.org/10.1155/2013/428078
Research Article

Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools

1INDI Department, Vrije Universiteit Brussel, 1050 Brussels, Belgium
2ELIS Department, Ghent University, 9000 Ghent, Belgium
3ETRO Department, Vrije Universiteit Brussel, 1050 Brussels, Belgium

Received 30 September 2013; Accepted 27 November 2013

Academic Editor: João Cardoso

Copyright © 2013 Bruno da Silva et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. S. Williams, A. Waterman, and D. Patterson, “Roofline: an insightful visual performance model for multicore architectures,” Communications of the ACM, vol. 52, no. 4, pp. 65–76, 2009. View at Publisher · View at Google Scholar · View at Scopus
  2. Y. Sato, R. Nagaoka, A. Musa et al., “Performance tuning and analysis of future vector processors based on the roofline model,” in Proceedings of the 10th Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture (MEDEA '09), pp. 7–14, ACM, September 2009. View at Publisher · View at Google Scholar · View at Scopus
  3. M. Reichenbach, M. Schmidt, and D. Fey, “Analytical model for the optimization of self-organizing image processing systems utilizing cellular automata,” in Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW '11), pp. 162–171, Newport Beach, Calif, USA, March 2011. View at Publisher · View at Google Scholar · View at Scopus
  4. J. A. Lorenzo, J. C. Pichel, T. F. Pena, M. Suarez, and F. F. Rivera, “Study of Performance Issues on a SMP-NUMA System using the Roofline Model,” in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA '11), Las Vegas, Nev, USA, 2011.
  5. H. Jia, Y. Zhang, G. Long, J. Xu, S. Yan, and Y. Li, “GPURoofline: amodel for guiding performance optimizations on GPUs,” in Proceedings of the 18th International Conference on Parallel Processing (Euro-Par '12), pp. 920–932, 2012. View at Publisher · View at Google Scholar
  6. K. H. Kim, K. Kim, and Q. H. Park, “Performance analysis and optimization of three-dimensional FDTD on GPU using roofline model,” Computer Physics Communications, vol. 182, no. 6, pp. 1201–1207, 2011. View at Publisher · View at Google Scholar · View at Scopus
  7. C. Nugteren and H. Corporaal, “The boat hull model: adapting the roofline model to enable performance prediction for parallel computing,” in Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'12), pp. 291–292, February 2012. View at Publisher · View at Google Scholar · View at Scopus
  8. M. Spierings and R. van de Voort, “Embedded platform selection based on the roofline model: applied to video content analysis,” 2012.
  9. B. da Silva, A. Braeken, E. H. D'Hollander, A. Touhafi, J. G. Cornelis, and J. Lemeire, “Performance and toolchain of a combined GPU/FPGA desktop,” in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '13), p. 274, 2013. View at Publisher · View at Google Scholar
  10. J. Park, P. C. Diniz, and K. R. S. Shayee, “Performance and area modeling of complete FPGA designs in the presence of loop transformations,” IEEE Transactions on Computers, vol. 53, no. 11, pp. 1420–1435, 2004. View at Publisher · View at Google Scholar · View at Scopus
  11. L. Deng, K. Sobti, Y. Zhang, and C. Chakrabarti, “Accurate area, time and power models for FPGA-based implementations,” Journal of Signal Processing Systems, vol. 63, no. 1, pp. 39–50, 2011. View at Publisher · View at Google Scholar · View at Scopus
  12. B. Holland, K. Nagarajan, and A. D. George, “RAT: RC amenability test for rapid performance prediction,” ACM Transactions on Reconfigurable Technology and Systems, vol. 1, no. 4, article 22, 2009. View at Publisher · View at Google Scholar
  13. J. Curreri, S. Koehler, A. D. George, B. Holland, and R. Garcia, “Performance analysis framework for high-level language applications in reconfigurable computing,” ACM Transactions on Reconfigurable Technology and Systems, vol. 3, no. 1, article 5, 2010. View at Publisher · View at Google Scholar
  14. S. Skalicky, S. Lopez, M. Lukowiak, J. Letendre, and M. Ryan, “Performance modeling of pipelined linear algebra architectures on FPGAs,” in Reconfigurable Computing: Architectures, Tools and Applications, pp. 146–153, Springer, Berlin, Germany, 2013. View at Google Scholar
  15. B. da Silva, A. Braeken, E. H. D'Hollander, and A. Touhafi, “Performance and resource modeling for FPGAs using high-level synthesis tools,” PARCO, 2013.
  16. S. Williams, J. Carter, L. Oliker, J. Shalf, and K. Yelick, “Optimization of a lattice Boltzmann computation on state-of-the-art multicore platforms,” Journal of Parallel and Distributed Computing, vol. 69, no. 9, pp. 762–777, 2009. View at Publisher · View at Google Scholar · View at Scopus
  17. J. Villarreal, A. Park, W. Najjar, and R. Halstead, “Designing modular hardware accelerators in C with ROCCC 2.0,” in Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM '10), pp. 127–134, Charlotte, NC, USA, May 2010. View at Publisher · View at Google Scholar · View at Scopus
  18. Z. Guo, B. Buyukkurt, and W. A. Najjar, “Input data reuse in compiling window operations onto reconfigurable hardware,” in Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES '04), pp. 249–256, June 2004. View at Scopus