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International Journal of Reconfigurable Computing
Volume 2013 (2013), Article ID 789134, 40 pages
http://dx.doi.org/10.1155/2013/789134
Research Article

Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs

1Graduate School of Information Science, Nagoya University, C3-1 (631) Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan
2Department of VLSI System Design, College of Science and Engineering, Ritsumeikan University, 1-1-1 Noji-Higashi Kusatsu, Shiga 525-8577, Japan

Received 28 February 2013; Revised 4 July 2013; Accepted 8 July 2013

Academic Editor: Michael Hübner

Copyright © 2013 Krzysztof Jozwik et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. P. Sedcole, B. Blodget, T. Becker, J. Anderson, and P. Lysaght, “Modular dynamic reconfiguration in Virtex FPGAs,” IEE Proceedings, vol. 153, no. 3, pp. 157–164, 2006. View at Publisher · View at Google Scholar · View at Scopus
  2. W. Fornaciari and V. Piuri, “Virtual FPGAs: some steps behind the physical barriers,” in Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS '98), 1998.
  3. G. Brebner, “A virtual hardware operating system for the Xilinx XC 6200,” in Proceedings of the IEEE International Conference on Field Programmable Logic and Applications (FPL '96), 1996.
  4. G. Brebner, “Automatic identification of swappable logic units in XC6200 circuitry,” in Proceedings of the IEEE International Conference on Field Programmable Logic and Applications (FPL '97), 1997.
  5. G. Wigley and D. Karney, “The first real operating system for reconfigurable computers,” in Proceedings of the Computer Systems Architecture Conference, 2001.
  6. P. A. Hsiung, M. D. Santambrogio, C. H. Huang et al., Reconfigurable System Design and Verification, CRC Press, 2008.
  7. B. Walder and M. Platzner, “A runtime environment for reconfigurable hardware operating systems,” in Proceedings of the IEEE International Conference on Field Programmable Logic and Applications (FPL '04), 2004.
  8. D. Andrews, D. Niehaus, R. Jidin et al., “Programming models for hybrid FPGA-CPU computational components: a missing link,” IEEE Micro, vol. 24, no. 4, pp. 42–53, 2004. View at Publisher · View at Google Scholar · View at Scopus
  9. H. Takada and K. Sakamura, “μITRON for small-scale embedded systems,” IEEE Micro, vol. 15, no. 6, pp. 46–54, 1995. View at Publisher · View at Google Scholar · View at Scopus
  10. Free Software Foundation. eCos Project, http://ecos.sourceware.org/.
  11. J. Cong, B. Liu, S. Neuendorffer, J. Noguera, K. Vissers, and Z. Zhang, “High-level synthesis for FPGAs: from prototyping to deployment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 4, pp. 473–491, 2011. View at Publisher · View at Google Scholar · View at Scopus
  12. A. Ismail and L. Shannon, “FUSE: front-end user framework for O/S abstraction of hardware accelerators,” in Proceedings of the 19th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM '11), pp. 170–177, May 2011. View at Publisher · View at Google Scholar · View at Scopus
  13. A. Ali, M. Jomaa, B. Romanous et al., “An operating system for a reconfigurable active SSD processing node,” in Proceedings of the 19th International Conference on Telecommunications (ICT '12), 2012.
  14. L. Ye, J.-P. Diguet, and G. Gogniat, “Rapid application development on multi-processor reconfigurable systems,” in Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL '10), pp. 285–290, September 2010. View at Publisher · View at Google Scholar · View at Scopus
  15. M. Ullmann, M. Hübner, B. Grimm, and J. Becker, “An FPGA run-time system for dynamical on-demand reconfiguration,” in Proceedings of the Reconfigurable Architectures Workshop (RAW '04), pp. 1841–1848, April 2004. View at Scopus
  16. M. D. Santambrogio, V. Rana, and D. Sciuto, “Operating system support for online partial dynamic reconfiguration management,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '08), pp. 455–458, September 2008. View at Publisher · View at Google Scholar · View at Scopus
  17. I. Beretta, V. Rana, M. D. Santambrogio, and D. Sciuto, “On-line task management for a reconfigurable cryptographic architecture,” in Proceedings of the 23rd IEEE International Parallel and Distributed Processing Symposium (IPDPS '09), May 2009. View at Publisher · View at Google Scholar · View at Scopus
  18. H. K.-H. So and R. Brodersen, “A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH,” Transactions on Embedded Computing Systems, vol. 7, no. 2, article 14, 2008. View at Publisher · View at Google Scholar · View at Scopus
  19. E. Lübbers and M. Platzner, “Reconos: an RTOS supporting hard- and software threads,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '07), pp. 441–446, August 2007. View at Publisher · View at Google Scholar · View at Scopus
  20. E. Lubbers and M. Platzner, “A portable abstraction layer for hardware threads,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '08), pp. 17–22, September 2008. View at Publisher · View at Google Scholar · View at Scopus
  21. D. Andrews, R. Sass, E. Anderson et al., “Achieving programming model abstractions for reconfigurable computing,” IEEE Transactions on Very Large Scale Integration, vol. 16, no. 1, pp. 34–43, 2008. View at Publisher · View at Google Scholar · View at Scopus
  22. MathWorks Simulink, http://www.mathworks.com/products/simulink.
  23. V. Nollet, P. Coene, D. Verkest et al., “Designing an operating system for a heterogeneous reconfigurable SoC,” in Proceedings of the IEEE International Parallel and Distributed Processing Symposium (IPDPS '03), 2003.
  24. TOPPERS project. Official website, http://www.toppers.jp/.
  25. C. Steiger, H. Walder, and M. Platzner, “Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks,” IEEE Transactions on Computers, vol. 53, no. 11, pp. 1393–1407, 2004. View at Publisher · View at Google Scholar · View at Scopus
  26. J. A. Clemente, J. Resano, C. González, and D. Mozos, “A Hardware implementation of a run-time scheduler for reconfigurable systems,” IEEE Transactions on Very Large Scale Integration, vol. 19, no. 7, pp. 1263–1276, 2011. View at Publisher · View at Google Scholar · View at Scopus
  27. F. Ghaffari, B. Miramond, and F. Verdier, “Run-time HW/SW scheduling of data flow applications on reconfigurable architectures,” Eurasip Journal on Embedded Systems, vol. 2009, Article ID 976296, 2009. View at Publisher · View at Google Scholar · View at Scopus
  28. F. Dittmann and S. Frank, “Hard real-time reconfiguration port scheduling,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07), pp. 123–128, fra, April 2007. View at Publisher · View at Google Scholar · View at Scopus
  29. F. Dittmann and S. Frank, “Caching in real-time reconfiguration port scheduling,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '07), pp. 740–744, August 2007. View at Publisher · View at Google Scholar · View at Scopus
  30. Y. Qu, J.-P. Soininen, and J. Nurmi, “Improving the efficiency of run time reconfigurable devices by configuration locking,” in Proceedings of the IEEE Conference on Design, Automation and Test in Europe (DATE '08), pp. 264–267, March 2008. View at Publisher · View at Google Scholar · View at Scopus
  31. D. Göhringer, M. Hübner, E. N. Zeutebouo, and J. Becker, “CAP-OS: operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures,” in Proceedings of the IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum (IPDPSW '10), April 2010. View at Publisher · View at Google Scholar · View at Scopus
  32. E. Lübbers and M. Platzner, “Cooperative multithreading in dynamically reconfigurable systems,” in Proceedings of the 19th International Conference on Field Programmable Logic and Applications (FPL '09), pp. 551–554, September 2009. View at Publisher · View at Google Scholar · View at Scopus
  33. Xilinx, Embedded Development Kit (Xilkernel), http://www.xilinx.com/tools/platform.htm.
  34. E. Lübbers and M. Platzner, “Communication and synchronization in multithreaded reconfigurable computing systems,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '08), pp. 83–89, July 2008. View at Scopus
  35. M. Vuletić, L. Pozzi, and P. Ienne, “Seamless hardware-software integration in reconfigurable computing systems,” IEEE Design and Test of Computers, vol. 22, no. 2, pp. 102–113, 2005. View at Publisher · View at Google Scholar · View at Scopus
  36. X. Iturbe, K. Benkrid, T. Arslan, R. Torrego, and I. Martinez, “Methods and mechanisms for hardware multitasking: executing and synchronizing fully relocatable hardware tasks in xilinx FPGAs,” in Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL '11), pp. 295–300, September 2011. View at Publisher · View at Google Scholar · View at Scopus
  37. K. Kosciuszkiewicz, F. Morgan, K. Kepa et al., “Run-time management of reconfigurable hardware tasks using embedded linux,” in Proceedings of the IEEE Computer Symposium on Emerging VLSI Technologies and Architectures, 2006.
  38. S. Mahadevan, V. S. Gopinath, R. Lysecky, J. Sprinkle, J. Rozenblit, and M. W. Marcellin, “Hardware/software communication middleware for data adaptable embedded systems,” in Proceedings of the 18th IEEE International Conference and Workshops on Engineering of Computer-Based Systems (ECBS '11), pp. 34–43, April 2011. View at Publisher · View at Google Scholar · View at Scopus
  39. S. Narayanan, D. Chillet, S. Pillement, and I. Sourdis, “Hardware OS communication service and dynamic memory management for RSoCs,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig '11), pp. 117–122, December 2011. View at Publisher · View at Google Scholar · View at Scopus
  40. J. Congfeng, “System level power characterization of multi-core computers with dynamic frequency scaling support,” in Proceedings of the International Conference on Cluster Computing Workshops, 2012.
  41. Intel, Enhanced Intel SpeedStep Technology For the Intel Pentium M Processor, White Paper, 2004.
  42. A. Tiwari, “A partial reconfiguration based approach for frequency synthesis using FPGA,” in Proceedings of the International Conference on Communication Technology and System Design (ICCTSD '11), 2011.
  43. C. Schuck, B. Haetzer, and J. Becker, “Reconfiguration techniques for self-X power and performance management on xilinx virtex-II/virtex-II-pro FPGAs,” International Journal of Reconfigurable Computing, vol. 2011, Article ID 671546, 2011. View at Publisher · View at Google Scholar · View at Scopus
  44. X. Iturbe, K. Benkrid, A. T. Erdogan et al., “R3TOS: a reliable reconfigurable real-time operating system,” in Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS '10), pp. 99–104, June 2010. View at Publisher · View at Google Scholar · View at Scopus
  45. X. Iturbe, K. Benkrid, R. Torrego et al., “Online clock routing in Xilinx FPGAs for high-performance and reliability,” in Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2012.
  46. Xilinx, “UG702 (v12. 3): partial reconfiguration user guide,” Tech. Rep., 2010. View at Google Scholar
  47. Altera, “Quartus II Handbook,” Tech. Rep., Design and Synthesis, 2012. View at Google Scholar
  48. K. Jozwik et al., “Comparison of preemption schemes for partially reconfigurable FPGAs,” IEEE Embedded Systems Letters, vol. 4, no. 2, 2012. View at Google Scholar
  49. A. Gerstlauer, C. Haubelt, A. D. Pimentel, T. P. Stefanov, D. D. Gajski, and J. Teich, “Electronic system-level synthesis methodologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1517–1530, 2009. View at Publisher · View at Google Scholar · View at Scopus
  50. H. Kalte and M. Porrmann, “REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs,” in Proceedings of the 3rd Conference on Computing Frontiers (CF '06), pp. 403–412, May 2006. View at Publisher · View at Google Scholar · View at Scopus
  51. T. Becker, W. Luk, and P. Y. K. Cheung, “Enhancing relocatability of partial bitstreams for run-time reconfiguration,” in Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '07), pp. 35–44, April 2007. View at Publisher · View at Google Scholar · View at Scopus
  52. J. Carver, “Relocation of FPGA partial configuration bit-streams for soft-core microprocessors,” in Proceedings of the Workshop on Soft Processor Systems, 2008.
  53. S. Corbetta, M. Morandi, M. Novati, M. D. Santambrogio, D. Sciuto, and P. Spoletini, “Internal and external bitstream relocation for partial dynamic reconfiguration,” IEEE Transactions on Very Large Scale Integration, vol. 17, no. 11, pp. 1650–1654, 2009. View at Publisher · View at Google Scholar · View at Scopus
  54. Xilinx, “UG070 (v2. 5): virtex-4 FPGA user guide,” Tech. Rep., 2008. View at Google Scholar
  55. K. Jozwik, H. Tomiyama, S. Honda, and H. Takada, “A novel mechanism for effective hardware task preemption in dynamically reconfigurable systems,” in Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL '10), pp. 352–355, September 2010. View at Publisher · View at Google Scholar · View at Scopus
  56. P. A. Laplante, Real-Time Systems Design and Analysis, Wiley-Interscience, IEEE Press, 3rd edition, 2004.
  57. Y Explorations eXCite., http://www.yxi.com/.
  58. C. E. Cummings, “Simulation and synthesis techniques for asynchronous FIFO design,” in Proceedings of the Synopsys Users Group Conference (SNUG '01), 2001.
  59. Xilinx, “DS302 (v3. 7): virtex-4 FPGA data sheet: DC and switching characteristics,” Tech. Rep., 2009. View at Google Scholar
  60. Y. Hara, H. Tomiyama, S. Honda et al., “Proposal and quantitative analysis of the chstone benchmark program suite for practical C-based high-level synthesis,” IPSJ Journal of Information Processing, vol. 17, pp. 242–254, 2009. View at Google Scholar
  61. NEC CyberWorkBench, http://www.nec.com/cyberworkbench.
  62. Xilinx, “Vivado Design Suite,” http://www.xilinx.com/vivado.