Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs

Table 6

Communication Channels' HW Interface Modules—synthesis results.

Interface module	Depth (word)	Slices	FFs	LUTs	FCLK freq. (MHz)	VCLK freq. (MHz)
SHD MEM RD + WR	1	317	242	403	215.4	263.8
	8	342	258	451	205.4	238.6
	32	554	293	730	196.1	213.9
	128	1459	350	1782	196.4	181.6
FIFO (MST-side write)	1	158	89	221	240.8	276.6
	8	173	97	251	210	254
	32	272	115	378	217.7	210.8
	128	721	144	897	182.8	208.2
FIFO (MST-side read)	1	190	130	262	238.1	328.5
	8	211	141	300	228.8	251.6
	32	325	159	455	209.4	227.5
	128	784	188	993	191.1	182.3
MSG (MST-side write)	1	160	96	225	244.7	276.6
	8	170	105	244	244.8	257.8
	32	271	121	375	214.6	211.5
	128	731	140	916	175.5	166.6
MSG (MST-side read)	1	196	135	274	235.3	328.5
	8	212	145	304	227.7	261.8
	32	332	164	468	203.5	234
	128	791	211	1006	214.5	219.5
FIFO (SLV-side write)	1	101	61	119	367.2	333.8
	8	112	74	139	283	283.8
	32	219	84	281	232	226.5
	128	679	102	819	179.4	166.4
FIFO (SLV-side read)	1	109	71	120	343	330
	8	123	87	149	311.8	277
	32	234	99	298	209.3	233
	128	692	123	833	188.5	180
MSG (SLV-side write)	1	104	63	124	363.2	333.8
	8	114	76	144	283	283.7
	32	221	86	286	232	226.5
	128	681	104	824	179.4	166.4
MSG (SLV-side read)	1	115	76	133	336.8	330
	8	130	92	162	311.7	277
	32	240	104	311	209.3	233
	128	698	123	845	172.8	180
REG (write)	1	65	111	80	431.6	370
REG (read)	1	85	148	16	874.1	632.3

Data width = 32.
Unless indicated otherwise, the values in the table are unitless.