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International Journal of Reconfigurable Computing
Volume 2013, Article ID 802436, 24 pages
Research Article

Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

1LIP6, Universite Pierre et Marie Curie, 4 Place Jussieu, 75252 Paris, France
2Flexras Technologies, 153 Boulevard Anatole France, 93200 Saint-Denis, France

Received 28 June 2013; Revised 11 October 2013; Accepted 16 October 2013

Academic Editor: Nadia Nedjah

Copyright © 2013 Emna Amouri et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-railsignals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in tree-based, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number.