Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

Table 2

Measured performance figures.

	Min.	Max.
Scheduling
Scheduling algorithm execution	<1 𝜇s	100 𝜇s
Queues and task state updating	<1 𝜇s	300 𝜇s
Allocation
Allocation algorithm execution	<1 𝜇s	100 𝜇s
Empty Area Descriptor updating	10 𝜇s	200 𝜇s
Inter-task communications
Transfer LUT data buffer (ICAP)	3.7 𝜇s	3.7 𝜇s
Transfer BRAM data buffer (ICAP)	60.18 𝜇s	60.18 𝜇s
Transfer BRAM data buffer (DRTS): configuration layer	36.18 𝜇s	39.9 𝜇s
Transfer BRAM data buffer (DRTS): functional layer	81.92 𝜇s	81.92 𝜇s
Switching brams between neighbor tasks	10.03 𝜇s	10.03 𝜇s
Inter-task synchronization
Polling of a HWS	1.6 𝜇s	1.6 𝜇s
Activation of a HWS	3.7 𝜇s	3.7 𝜇s