Research Article

Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration

Table 2

Implementation results for square root and inverse square root logic.

Method Proposed method NR + CORDIC method [4, 5] CORDIC method [8]

Slice registers 160 296 877
Slice LUTs 160 556 978
DSP48Es 4 3 1
BRAMs 1 1 0
Latency 5 10 41
Operating frequency (MHz) 351.865 234.917 200.88
Mean error for isqrt
Mean error for sqrt