Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration

Table 3

Implementation results for the processing elements.

	Boundary cell	Internal cell
Type		Fine grain pipelining	Register in path
Resources	Number used
Slice registers	289	0	32
Slice LUTs	209	17	17
DSP48Es	5	2	2
BRAMs	1	0	0
Operating frequency (MHz)	220.43	177.35	161.773
Latency	11	1	1