IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance

Table 11

Configurable parameters in Xilinx CORDIC IP core.

Configurable parameter (attribute)	Possible values (attribute values) (to select one)
Functional selection	Rotate, translate, sin and cos, sinh and cosh, arc tan, arc tanh, square root
Architectural configuration	Word serial, parallel
Pipelining mode	No pipelining, optimal, maximum
Data format	Signed fraction, unsigned fraction, unsigned integer
Phase format	Radians, scaled radians
Input width	Range 8 to 48
Output width	Range 5 to 48
Round mode	Truncate, round positive infinity, round positive negative infinity, nearest even
Iterations	Range 0 to 48
Precision	Range 0 to 48
Coarse rotation	Yes, no
Compensation scaling	No scale compensation, Lut based, Bram based, embedded multiplier