Research Article
IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance
Table 9
Mapping of exponential decay formula.
| | Design | XC7VX330T-1FFG1157 | | I/P data | LUT | FF | DSP | SRL | BRAM | CLK (ns)9 | Latency/throughput | IP core |
| | exp-decay (v-HLS) | SP FP | 2656 | 2147 | 40 | 237 | 0 | 4.486 | 56/56 | No | | exp-decay (proposed)-D1 | SP FP | 4539 | 4679 | 8 | 39/
4539 | 0 | 2.649 | 61/30 | Yes | | exp-decay (proposed)-D2 | SP FP | 4633 | 4807 | 6 | 65/
4633 | 0 | 2.618 | 63/32 | Yes | | exp-decay (proposed)-D3 | SP FP | 4561 | 4566 | 8 | 17/
4561 | 0 | 4.568 | 57/26 | Yes | | exp-decay (proposed)-D4 | SP FP | 4571 | 4675 | 6 | 45/
4675 | 0 | 2.725 | 61/30 | Yes | | exp-decay (proposed)-D5 | SP FP | 4539 | 4679 | 8 | 39/4539 | 0 | 2.649 | 26/20 | Yes |
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Clock period constraint of 5 ns with zero input jitter.
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