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International Journal of Reconfigurable Computing
Volume 2014, Article ID 502942, 15 pages
Research Article

FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

Dalian Institute of Semiconductor Technology and School of Electronic Science and Technology, Dalian University of Technology, Dalian 116023, China

Received 27 June 2014; Revised 3 August 2014; Accepted 6 August 2014; Published 31 August 2014

Academic Editor: Nadia Nedjah

Copyright © 2014 Kaiyu Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Spazhakin Michael Igorevich, and Tokarev Anton Borisovich, “Digital receiver for addressed direction finding of modern communication standards,” 2015 International Siberian Conference on Control and Communications (SIBCON), pp. 1–4, . View at Publisher · View at Google Scholar
  • Sérgio Bimbi Junior, Vitor Chaves De Oliveira, and Gunnar Bedicks Junior, “Software defined radio implementation of a QPSK modulator/demodulator in an extensive hardware platform based on FPGAs Xilinx ZYNQ,” Journal of Computer Science, vol. 11, no. 4, pp. 598–611, 2015. View at Publisher · View at Google Scholar
  • Mehdi Ayat, Sattar Mirzakuchaki, and AliAsghar Beheshti-Shirazi, “Design and Implementation of High Throughput, Robust, Parallel M-QAM Demodulator in Digital Communication Receivers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 8, pp. 1295–1304, 2016. View at Publisher · View at Google Scholar