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International Journal of Reconfigurable Computing
Volume 2014 (2014), Article ID 564924, 14 pages
http://dx.doi.org/10.1155/2014/564924
Research Article

Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

1School of Computer Engineering, Nanyang Technological University, Singapore 639798
2The Hong Kong University of Science and Technology, Hong Kong

Received 9 May 2014; Revised 22 September 2014; Accepted 7 October 2014; Published 21 October 2014

Academic Editor: Michael Hübner

Copyright © 2014 Sharad Sinha and Thambipillai Srikanthan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Sharad Sinha and Thambipillai Srikanthan, “Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis,” International Journal of Reconfigurable Computing, vol. 2014, Article ID 564924, 14 pages, 2014. doi:10.1155/2014/564924