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International Journal of Reconfigurable Computing
Volume 2014, Article ID 564924, 14 pages
http://dx.doi.org/10.1155/2014/564924
Research Article

Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

1School of Computer Engineering, Nanyang Technological University, Singapore 639798
2The Hong Kong University of Science and Technology, Hong Kong

Received 9 May 2014; Revised 22 September 2014; Accepted 7 October 2014; Published 21 October 2014

Academic Editor: Michael Hübner

Copyright © 2014 Sharad Sinha and Thambipillai Srikanthan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. “Xtreme DSP for Virtex-4 FPGAs User Guide,” UG073(v2.7), 2008.
  2. Virtex-6 FPGA DSP48E1 Slice User Guide, UG369(v1.3), 2011.
  3. 2013, http://www.altera.com/devices/fpga/stratix-fpgas/about/dsp/stx-dsp-block.html.
  4. 2014, http://en.wikipedia.org/wiki/Molecular_dynamics.
  5. M. J. Wirthlin, “Constant coefficient multiplication using look-up tables,” Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 36, no. 1, pp. 7–15, 2004. View at Publisher · View at Google Scholar · View at Scopus
  6. N. Boullis and A. Tisserand, “Some optimizations of hardware multiplication by constant matrices,” IEEE Transactions on Computers, vol. 54, no. 10, pp. 1271–1282, 2005. View at Publisher · View at Google Scholar · View at Scopus
  7. P. K. Meher, “LUT optimization for memory-based computation,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 4, pp. 285–289, 2010. View at Publisher · View at Google Scholar · View at Scopus
  8. Y. Voronenko and M. Puschel, “Multiplierless multiple constant multiplication,” ACM Transactions on Algorithms, vol. 3, no. 2, article 11, 2007. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  9. P. Tummeltshammer, J. C. Hoe, and M. Püschel, “Time-multiplexed multiple-constant multiplication,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 9, pp. 1551–1563, 2007. View at Publisher · View at Google Scholar · View at Scopus
  10. R. Gutierrez, J. Valls, and A. Perez-Pascual, “FPGA-implementation of time-multiplexed multiple constant multiplication based on carry-save arithmetic,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '09), pp. 609–612, Prague, Czech Republic, September 2009. View at Publisher · View at Google Scholar · View at Scopus
  11. S. S. Demirsoy, I. Kale, and A. G. Dempster, “Synthesis of reconfigurable multiplier blocks: part I—fundamentals,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS ’05), vol. 1, pp. 536–539, May 2005. View at Publisher · View at Google Scholar
  12. S. S. Demirsoy, I. Kale, and A. G. Dempster, “Synthesis of reconfigurable multiplier blocks: part I—algorithm,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '05), pp. 540–543, May 2005. View at Publisher · View at Google Scholar · View at Scopus
  13. F. de Dinechin and B. Pasca, “Large multipliers with fewer DSP blocks,” in Proceedings of the 19th International Conference on Field Programmable Logic and Applications (FPL '09), pp. 250–255, September 2009. View at Publisher · View at Google Scholar · View at Scopus
  14. F. de Dinechin and B. Pasca, “Large multipliers with less DSP blocks,” LIP Research Report RR2009-03, 2009. View at Google Scholar
  15. A. Karatsuba and O. Yu, “Multiplication of multidigit numbers on automata,” Soviet Physics Doklady, vol. 7, no. 7, pp. 595–596, 1963. View at Google Scholar
  16. Implementing Multipliers in FPGA Devices, Altera Application Note, AN 306(ver 3.0), July 2004.
  17. A. K. Verma and P. Ienne, “Towards the automatic exploration of arithmetic-circuit architectures,” in Proceedings of the Design Automation Conference (DAC '06), pp. 445–450, 2006.
  18. R. Ruiz-Sautua, M. C. Molina, J. M. Mendías, and R. Hermida, “Pre-synthesis optimization of multiplications to improve circuit performance,” in Proceedings of the Design, Automation and Test in Europe (DATE '06), vol. 1, pp. 1–6, Munich, March 2006. View at Publisher · View at Google Scholar · View at Scopus
  19. Virtex-5 FPGA XtremeDSP Design Considerations User Guide, UG193 (v3.5), 2012.
  20. D. Kulkarni, W. A. Najjar, R. Rinker, and F. J. Kurdahi, “Compile-time area estimation for LUT-based FPGAs,” ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 1, pp. 104–122, 2006. View at Publisher · View at Google Scholar · View at Scopus
  21. T. Jiang, X. Tang, and P. Banerjee, “Macro-models for high level area and power estimation on FPGAs,” in Proceedings of the 14th ACM Great lakes Symposium on VLSI (GLSVLSI '04), pp. 162–165, April 2004. View at Scopus
  22. G. A. Constantinides and G. J. Woeginger, “The complexity of multiple wordlength assignment,” Applied Mathematics Letters, vol. 15, no. 2, pp. 137–140, 2002. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  23. M.-A. Cantin, Y. Savaria, D. Prodanos, and P. Lavoie, “A metric for automatic word-length determination of hardware datapaths,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 2228–2231, 2006. View at Publisher · View at Google Scholar · View at Scopus
  24. L. Zhang, Y. Zhang, and W. Zhou, “Fast trade-off evaluation for digital signal processing systems during wordlength optimization,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '09), pp. 731–738, San Jose, Calif, USA, November 2009. View at Scopus
  25. Vivado-HLS User Guide, UG 910 (v 2013.2), June 2013.
  26. XST User Guide for Virtex-4, Virtex-5, Spartan-3 and Newer CPLD Devices, UG627(v 14.5), 2013.