Simple Hybrid Scaling-Free CORDIC Solution for FPGAs

Table 2

FPGA implementation results of conventional and hybrid algorithms.

	Conventional CORDIC	Hybrid CORDIC	Ratio (%)
Pipeline stages	16	9	56
Logic elements (ALUTs)	984	372	38
DSP blocks	0	8	—
Latency (nsec.)	50	29	58
Throughput (10^6/sec)	320	306	96