Hardware-Efficient Design of Real-Time Profile Shape Matching Stereo Vision Algorithm on FPGA

Table 1

Published FPGA implementation of stereo vision algorithms. FPGA resource usage is given, for those publications that provide it, in terms of percentage of configurable logic (%L) and percentage of memory (%M) for the specific device. The one exception is the BP implementation by Pérez et al. [28] which required a device with access to a total of 1.5 GB of memory.

Algorithm	fps	𝑊×𝐻 (disp)	%L/%M	FPGA
SAD (FPGA) [29]	599	450 × 375 (60)	57/11	Quartus II
RTSVP [30]	303	640 × 480 (60)	34/26	Stratix II EP2S60
11 × 11 census [18]	230	640 × 480 (60)	57/95	Virtex4 XC4VLX200
SymDP (FPGA) [31]	30	1024 × 768 (128)	—/—	Stratix III
Tyzx [32]	200	512 × 480 (52)	—/—	DSP, FPGA, Tyzx
MeanCensus [33]	130	640 × 480 (60)	27/4	Stratix 1S40
7 × 7 SAD [34]	25	512 × 512 (255)	44/—	Virtex4 XC4VLX15
CensusVarCross [16]	62	640 × 480 (60)	—/—	Stratix III EP3SL150
SAD-IGMCT [17]	62	750 × 400 (60)	—/—	N/A
SAD left-right [35]	20	640 × 480 (80)	21/—	N/A
LWPC [36]	30	640 × 480 (36)	—/—	4 x Stratix S80
Trellis [37]	30	320 × 240 (128)	—/—	Virtex II pro-100
BP [28]	2	1280 × 720 (96)	12/1.5 G	Virtex 5 330VLX
Fasttrack DPML [38]	86	384 × 288 (16)	—/—	N/A
PARTS [39]	42	320 × 240 (24)	—/—	PARTS
Trinocular [40]	30	320 × 240 (32)	—/—	Virtex II XC2VP40
Adaptive census [41]	68	640 × 480 (—)	67/4	Virtex 6 VLX760