Multi-Softcore Architecture on FPGA

Table 7

Related work.

Reference	Author	Year	CPU type	# cores	Network	Memory architecture	Tested application
[30]	Li et al.	2003	FPGA-based massively parallel SIMD processor	95 simple processors	—	—	RC4 key search engine
[23]	Kissler et al.	2006	Parameterizable coarse-grained reconfigurable architecture	Parametric number of weakly programmable PEs	Different interconnect topologies (Torus, 4D hypercube, etc.)	—	—
[18]	Ruchandani and Rawat	2008	CBEA	8 PEs + PowerPC	Elementary interconnect bus (EIB)	Shared memory; Shared memory	Spatial domain filter
[22]	Wittenbrink et al.	2011	Fermi proc (GPGPU)	512	—	Shared memory	Gaming and high-performance computing
[25]	Melpignano et al.	2012	P2012 (MIMD)	Multiple clusters; one cluster can have from 1 to 16 PEs	Asynchronous global NoC	Shared memory	Extraction and tracking algorithms
[29]	Waidyasooriya et al.	2012	Heterogeneous multicore architecture	SIMD-1D 8 PE array and MIMD-2D PE array accelerators	Crossbar	Shared memory	M-M multiplication
[31]	Wjcik and Dlugopolski	2013	Application-specific multicore architecture	4 parallel processors	—	Shared parallel memory	Cipher algorithm
[24]	Lari et al.	2014	Massively parallel programmable accelerator	Parametric number of tightly coupled PEs	Circuit-switched Mesh-like interconnect	Multiple buffer banks	Loop computations
	Proposed work	2014	FPGA-based multicore SoC	Parametric number of cores	Crossbar	Local private memory	FIR filter; Laplacian filter; M-M multiplication