Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

Table 2

Synthesis results for CONNECT and SOTA mesh network [7].

4 × 4 mesh w/4 VCs	Xilinx LX240T		Xilinx LX760
	LCs	MHz	LCs	MHz
SOTA [11] (32-bit)	36%	158	12%	181
CONNECT [12] (32-bit)	15%	101	5%	113