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International Journal of Reconfigurable Computing
Volume 2015 (2015), Article ID 749816, 10 pages
Research Article

Leakage Immune Modified Pass Transistor Based 8T SRAM Cell in Subthreshold Region

Department of Electrical and Electronics Engineering, BITS, Pilani, Rajasthan 333031, India

Received 2 June 2015; Accepted 16 August 2015

Academic Editor: Martin Margala

Copyright © 2015 Priya Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The paper presents a novel 8T SRAM cell with access pass gates replaced with modified PMOS pass transistor logic. In comparison to 6T SRAM cell, the proposed cell achieves 3.5x higher read SNM and 2.4x higher write SNM with 16.6% improved SINM (static current noise margin) distribution at the expense of 7x lower WTI (write trip current) at 0.4 V power supply voltage, while maintaining similar stability in hold mode. The proposed 8T SRAM cell shows improvements in terms of 7.735x narrower spread in average standby power, 2.61x less in average (write access time), and 1.07x less in average (read access time) at supply voltage varying from 0.3 V to 0.5 V as compared to 6T SRAM equivalent at 45 nm technology node. Thus, comparative analysis shows that the proposed design has a significant improvement, thereby achieving high cell stability at 45 nm technology node.