Exploring Trade-Offs between Specialized Dataflow Kernels and a Reusable Overlay in a Stereo Matching Case Study

Table 1

Hardware resources of the two FPGA platforms as used in our experiments. Maxeler MAX3424A memory clock and bandwidth depend on user design. Convey HC-1 access granularity depends on installed DIMMs.

Platform	Maxeler MAX3424A	Convey HC-1
Application FPGAs	1 × Virtex-6 SX475T	4 × Virtex-5 LX330
#6-input LUTs	297600	4 × 207360 = 829440
#36 Kb BRAMs	1064	4 × 288 = 1152
#DIMMs	6	16
Memory controllers	On user FPGA	8 dedicated FPGAs
Memory clock	300 MHz, variable	300 MHz, fixed
Peak bandwidth	28.8 GB/s	74.4 GB/s
Min. access size	384 bytes	8 bytes