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Research Article
International Journal of Reconfigurable Computing
Volume 2016, Article ID 3015403, 3 pages
Letter to the Editor

Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”

Digital Technology Group, University of Kassel, 34121 Kassel, Germany

Received 15 March 2016; Accepted 14 July 2016

Academic Editor: Martin Margala

Copyright © 2016 Martin Kumm and Peter Zipf. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This brief points out some problems when mapping the optimized GPCs using the heuristic of the paper above. A thorough analysis revealed that a significant number of additional LUTs are required to route the signals when mapping the optimized designs on current FPGAs. Taking these resources into account, the optimized GPCs require at least the same resources as previous state of the art.