Research Article
FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture
Table 1
Operation codes for unified Add/Sub/Mul unit.
| Logic operation | Opcode | Shared logic | Unshared logic |
| GF addition | 00 | | ā | GF subtraction | 01 | | ā | GF multiplication | 10 | | |
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