International Journal of Reconfigurable Computing / 2016 / Article / Tab 5

Research Article

FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture

Table 5

Performance comparison with exiting FPGA implementations.

Design Field sizePlatformArea (slices)Freq (MHz)Time (ms)TP (Kbps)

This work160Virtex-47,088531.4114
1928,590482.383.5
22410,800433.564
25613,15840551

This work160Virtex-II pro6,492401.984
1927,930353.260
2249,308314.945
25611,104277.434

[21] 160Virtex-412,415602.272
19214,858533.555
22417,331475.441
25620,123437.733

[18] 160Virtex-II3,433407.122
1924,1353511.616.5
2244,8083316.813.3

[16] 192Virtex-II pro20,793497.2426
[32] 192Virtex-II pro3,173939.9019.3
[33] 256Virtex-II pro15,775395.9942.7

[20] 192Virtex-II pro8,972434.4742
22410,386406.5034
25611,953369.3827.2

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