International Journal of Reconfigurable Computing

Volume 2016, Article ID 9128683, 8 pages

http://dx.doi.org/10.1155/2016/9128683

## XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware

^{1}Department of EEE, BITS-Pilani, Pilani, Rajasthan 333031, India^{2}Digital System Group, CEERI, Pilani, Rajasthan 333031, India

Received 30 September 2015; Accepted 11 January 2016

Academic Editor: Miriam Leeser

Copyright © 2016 Gaurav Purohit et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW) implementation of new architecture uses Lookup Table (LUT) for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.

#### 1. Introduction

Data transmission reliability and stringent QoS requirements of modern 3GPP, 3GPP2, and LTE standards over unreliable wireless channel require efficient, cost-effective forward error correction (FEC) codes for the mobile equipment [1–4]. The usage and application of such FEC depend mainly on their error correcting capabilities and power efficient implementation. Convolution codes are preferred over block codes due to their economical soft decoding capability and, moreover, they yield higher coding gain [5]. While the error correction capabilities are related to polynomial strength, they are also designed to achieve higher free distance [6]. The conventional convolutional encoder is usually realized with shift register (SR) using delay elements and modulo-2 adders (XOR gates). The key operation in the process of convolution is multiplication, which is implemented using shifts and additions [7]. The addition operation dominates the complexity in comparison to the shift operations and consumes a significant amount of dynamic power while encoding. Hence, the optimization of adder utilization becomes a key factor while implementing with reconfigurable hardware. Few attractive heuristic approaches are reported in the literature to minimize adder count by eliminating the redundant computations [8–13]. Such approaches are mostly based on Common Subexpression Elimination (CSE) method which depends upon the commonalities of the used polynomials involving modulo-two adders and consumes more power.

Convolution codes find their extensive usage as channel codes in popular wireless standards like 3GPP-WCDMA, 3GPP2-CDMA2000, LTE, and IEEE-802.11 and software defined radio and cognitive radio applications. They are the key building blocks in many powerful concatenated codes, such as Turbo codes (parallel), Woven codes (serial) [14], and Ungerboeck Code (a.k.a. Trellis Coded Modulation (TCM)) [15]. This paper describes a new algorithm to implement an XOR-FREE architecture of a chosen generator polynomial having constraint length () for popular wireless standards. The approach reduces the standard polynomial into a LUT comprising parity bits. The previous state of the encoder and the input bit jointly forms the decoding addresses of such LUT. The ROM based architecture provides ease in FPGA implementation with a powerful add-on feature of dynamic reconfiguration. The FPGAs have large resources of logic gates and ROM blocks. Hence, the hardware realization of this architecture is inferred in the desired approach and achieves greater flexibility. The paper is organized into five sections. In Section 2, the preliminary of the convolutional code is presented with two different approaches. Section 3 covers in depth a new algorithm with an example of GSM-900 based standard generator polynomial. Section 4 states the results and discussion, whereas Section 5 provides a conclusion.

#### 2. Preliminary

For realization of convolutional code, the theory of groups and finite fields is used. Two approaches are found in the literature. The first approach is taken by Massey [16] and McEliece and Onyszchuk [17]. The method defines the code first, as a -dimensional subspace of an -dimensional vector space over a suitable field, and then defines the encoder as a matrix whose rows are a basis for the code. Such a convolutional code can be described by an “infinite matrix, ” as shown in (1). This matrix depends on , , submatrices: Here, is the constraint length and are the generator sequences of the encoder. are the th block of information bits. are the block of coded bits at the output. This is similar to the block coding, , as shown inThe second approach is based on Forney’s approach which defines the encoder as a -input, -output linear, sequential circuit [18, 19] and can be realized by shift register as follows: where are elements of matrix . Equation (3) can be expanded explicitly in components, that is, as shown in (4). Obviously, shift register of length will have different internal configurations or states. The behavior of such convolutional coder depends upon the present input and previous input blocks . can be calculated by memorizing input values in shift registers as expressed in (5). Here, one register , for each bit of the input and memories for which are connected to adder *β*. Such realization of convolutional encoder can be captured by a Deterministic Finite State Machine (DFSM) or deterministic automaton [20].

Using (5) shift register based realization of the convolutional encoder for a used generator polynomial can be obtained as shown in Figure 1. A combination of sequential logic and combinational logic is required in the shift register based realization. The convolution encoder as a sequential machine can be presented as an FSM with the finite states. While working for optimal synthesis of sequential circuit, the approaches like state minimization and the state assignment exist, whereas for the combinational circuit, the logic minimization based on different topologies, namely, AND-OR or AND-XOR decomposition of functions, is available.