International Journal of Reconfigurable Computing / 2017 / Article / Tab 2

Research Article

Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection

Table 2

Device utilization and maximum operating speed.

Device nameMaximum speed (MHz)BRAMDSP48EFFLUT

Artix7-Xc7a100t csg324-188.33312269843
Artix7 Xc7a100t csg324-290.90912269843
Artix7 Xc7a100t csg324-3100.0012269843
Kintex7 Xc7k160t fbg484-1100.0012269843
Kintex7 Xc7k160 tfbg484-2111.11112269843
Kintex7 Xc7k160 tfbg484-3125.0012269843

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