Table 3: Results compared with [22] for the 16 × 16-digit pipelined multiplier.

# of pipeline
stages
[22] Proposed Comparison
Total delay (ns)Clock cycle (ns)#LUTsTotal delay (ns)Clock cycle (ns)#LUTsDelay reduction (%)Clock cycle time reduction (ns)# of LUT saving (%)

527.4005.480643819.0253.805684330.5730.57−6.29
628.7404.830666422.2423.707691822.6123.25−3.81
730.6604.460599228.3924.05669537.409.06−16.04