Research Article

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Table 10

Comparative survey of the state-of-the-art. Note that, while there are multiple implementation case studies in [19, 21], we only list here those cases which are the closest in terms of the QC-LDPC code used in our case study, namely the IEEE 802.11n (WiFi) (1944, 972) QC-LDPC code with . Development time (wherever reported) quantifies the programming effort required. This measure of the programming effort has been defined in [20] and is adopted here to facilitate an unambiguous comparison. In our work, the development effort is of the order of a few days of programming effort, once the algorithm to be implemented is finalized; including the total compile time which is of the order of tens of minutes.

Work Andrade et al. [19]Pratas et al. [20]Andrade et al. [21]Scheiber et al. [22]This work

HLS TechnologyAltera
OpenCL
Maxeler
MaxCompiler
Altera
OpenCL
Xilinx
Vivado HLS
National Instruments
LabVIEW FPGA Compiler
StandardIEEE WiMAXETSI DVB-S2IEEE WiFiIEEE WiFiIEEE WiFi
LDPC Parameters
BP Decoding Schedulefloodingfloodingfloodinglayeredserial and layered
Throughput (Mb/s)103.95402113.4608
Decoding Iterations10101034
Developement n.a.~weeksn.a.n.a.~days
FPGA DeviceAltera
Stratix 5 D5
Xilinx
Virtex-5 LX330T
Altera
Stratix 5 D5
Xilinx
Spartan-6 LX150T
Xilinx
Kintex-7 K410T
Fixed-point Precision (total bits)8n.a.n.a.n.a.10
Clock Rate (MHz)222.6150157122200
LUT (%)42.9n.a.4138.2
FF (%)42.3n.a.3625.3
BRAM (%)75.3n.a.6720.96.4
DSP (%)3.8n.a.005.2

n.a.: not available (i.e. not reported in the cited work).