Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language

Figure 26

Double buffering used between the ADC or DSP output and Gbe input. (a) Writing DSP samples to BUFFER 1 and creating a data packet by concurrent reading of BUFFER 2 samples. (b) Writing DSP samples to BUFFER 2 and creating a data packet by concurrent reading of BUFFER 1 samples.