Research Article

Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language

Table 1

IP core benchmark results for Xilinx, OpenCores, and SDR cores.

Source CoresSlices (23038)%LUTs (92152)%Registers (184304)%RAM (21680)%DSP48A1s (180)%BUFGs (16)%Maximum Clock Frequency (MHz)

Xilinx libraryFIR3015019611311111303
FFT88532294234031607216811141
DDC6802122312179147227311134

OpenCoresFIR155663872469110021111180
IIR2471857186410072401166
FFT120952768331201102441681184

SDR coresFIR4311321304100301611130
IIR1441376149210036201194
FFT93042518212671642216811118
DDC140464024451792002111129

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FMC15063121335112721142100850184
FM Rec.140464024451792002116154