A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Algorithm 1

Force-Directed Fault-Tolerance-Aware (FD-FTA) heuristic.

Input: Dataflow graph , latency constraint , error correction constraint

Output: Solution that minimizes resources

begin

Step 1. Triplicate into ;

Step 2. Schedule the operators of with constraint to obtain ;

Step 3. Bind the operators of with constraint to obtain ;

Step 4. Return solution from and ;

end