A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

<div>Illustrations of different structures used in Force-Directed Scheduling. The diagram in (a) shows the ASAP and ALAP schedule of a DFG and the respective time frames of the operations. The chart in (b) shows the distribution graph assuming both operations use the same resource type.</div>

International Journal of Reconfigurable Computing

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Figure 2

Figure 2: A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance 