A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Figure 5

Sample binding for a latency constraint of 4 cycles and error constraint of 50%. The binding in (a) depicts the first stage of binding, whereas the bindings in (b) and (c) represent bindings following different steps in the second stage. The binding in (b) depicts the merging of a singleton with a nonsingleton, and the binding in (c) depicts the merging of a pair of singletons.

(a)

(b)

(c)