Journals
Publish with us
Publishing partnerships
About us
Blog
International Journal of Reconfigurable Computing
Journal overview
For authors
For reviewers
For editors
Table of Contents
Special Issues
International Journal of Reconfigurable Computing
/
2017
/
Article
/
Fig 8
/
Research Article
A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance
Figure 8
Execution times of the three approaches in the benchmark set under a 2x normalized latency constraint and a 100% EC constraint.